H8SSLASH2218 datasheet(281/750 Pages) RENESAS

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Section 8 I/O Ports

Rev.6.00 Jun. 03, 2008 Page 233 of 698

REJ09B0074-0600

8.6

Port A

In the H8S/2218 Group, the port A is a 4-bit I/O port also functioning as address bus (A19 to A16)

output pins and SCI I/O pins. In the H8S/2212 Group, the port A is a 3-bit I/O port also

functioning as SCI I/O pins. The port A has the following registers.

• Port A data direction register (PADDR)

• Port A data register (PADR)

• Port A register (PORTA)

• Port A pull-up MOS control register (PAPCR)

• Port A open-drain control register (PAODR)

8.6.1

Port A Data Direction Register (PADDR)

PADDR specifies input or output for the pins of the port A.

Since PADDR is a write-only register, the bit manipulation instructions must not be used to write

PADDR. For details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.

Bit

Bit Name Initial Value

R/W

Description

7 to

⎯

Undefined

⎯

Reserved

These bits are undefined and cannot be modified.

PA3DDR

PA2DDR

PA1DDR

PA0DDR*

(H8S/2218 Group)

Modes 4 to 6:

If address output is enabled by the setting of bits AE3 to

AE0 in PFCR, the corresponding port A pins are address

outputs. When address output is disabled, setting a

PADDR bit to 1 makes the corresponding port A pin an

output port, while clearing the bit to 0 makes the pin an

input port.

Mode 7:

Setting a PADDR bit to 1 makes the corresponding port A

pin an output port, while clearing the bit to 0 makes the

pin an input port.

(H8S/2212 Group)

Setting a PADDR bit to 1 makes the corresponding port A

pin an output port, while clearing the bit to 0 makes the

pin an input port.

Note: * Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read. This bit

cannot be modified.

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