H8SSLASH2218 datasheet(282/750 Pages) RENESAS

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Section 8 I/O Ports

Rev.6.00 Jun. 03, 2008 Page 234 of 698

REJ09B0074-0600

8.6.2

Port A Data Register (PADR)

PADR stores output data for the port A pins.

Bit

Bit Name Initial Value

R/W

Description

7 to

⎯

Undefined

⎯

Reserved

These bits are undefined and cannot be modified.

PA3DR

PA2DR

PA1DR

PA0DR*

R/W

Store output data for a pin that functions as a general

output port.

Note: * Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read. This bit

cannot be modified.

8.6.3

Port A Register (PORTA)

PORTA indicates the pin states of the port A.

Bit

Bit Name Initial Value

R/W

Description

7 to

⎯

Undefined

⎯

Reserved

These bits are undefined.

PA3

PA2

PA1

PA0*

⎯*1

If the port A is read while PADDR bits are set to 1, the

PADR value is read. If the port A is read while PADDR

bits are cleared to 0, the pin states are read.

Notes: 1. Determined by the states of pins PA3 to PA0.

2. Reserved in the H8S/2212 Group. If this bit is read, an undefined value will be read.

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