SH7708 datasheet(122/633 Pages) RENESAS

122 / 633 page

104

In the address field, specify the entry address for selecting the entry (bits 10–4), W for selecting

the way (bits 12–11: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3 in normal mode (8-kbyte

cache); 00 and 10 are way 0, and 01 and 11 are way 1 in RAM mode), and H'F0 to indicate

address array access (bits 31–24).

When writing, specify bit 3 as the A bit. The A bit indicates whether addresses are compared

during writing. When the A bit is 1, the addresses of the four entries selected by the entry

addresses are compared to the addresses to be written into the address array specified in the data

field. Writing takes place to the way that has a hit. When a miss occurs, nothing is written to the

address array and no operation occurs. The way number (W) specified in bits 12–11 is not used.

When the A bit is 0, it is written to the entry selected with the entry address and way number

without comparing addresses. The address specified by bits 31–10 in the data specification in

figure 5.5 (1), address array access, is a virtual address. When the MMU is enabled, the address is

translated into a physical address, then the physical address is used in comparing addresses when

the A bit is 1. The physical address is written into the address array.

When reading, the address tag, V bit, U bit, and LRU bits of the entry specified by the entry

address and way number (W) are read using the data format shown in figure 5.5 without

comparing addresses. To invalidate a specific entry, specify the entry by its entry address and way

number, and write 0 to its V bit. To invalidate only an entry for an address to be invalidated,

specify 1 for the A bit.

When an entry for which 0 is written to the V bit has a U bit set to 1, if it is a valid entry it will be

written back. This allows coherency to be achieved between the external memory and cache by

invalidating the entry. However, when 0 is written to the V bit, 0 must also be written to the U bit

of that entry.

In the SH7708 Series, the top 3 bits of the 32-bit physical address are treated as a shadow (see

section 10, Bus State Controller (BSC)). Therefore, in the event of a cache miss, 0 is registered in

the top 3 bits of the address array address tag.

When directly changing the address array using the MOV instruction, also, a value other than 0

must not be set in the top 3 bits of the address tag.

5.4.2

Data Array

The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit

address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.

The address field specifies information for selecting the entry to be accessed; the data field

specifies the longword data to be written to the data array (figure 5.5 (2)).

In the address field, specify the entry address for selecting the entry (bits 10–4), L for indicating

the longword position within the (16-byte) line (bits 3–2: 00 is longword 0, 01 is longword 1, 10 is

longword 2, 11 is longword 3), W for selecting the way (bits 12–11: 00 is way 0, 01 is way 1, 10

SH7708 数据表(PDF) 122 Page - Renesas Technology Corp

SH7708 数据表(HTML) 122 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载