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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SH7708 数据表(PDF) 124 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 124 Page - Renesas Technology Corp |
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124 / 633 page  106 5.5 Usage Examples 5.5.1 Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a match is found. If no match is found, there is no operation. R0 specifies the write data in R0 and R1 specifies the address. When the V bit of an entry in the address array is set to 0, the entry is written back if the entry’s U bit is 1. ; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0 ; R1=H'F0000088; address array access, entry=B'0001000, A=1 ; MOV.L R0,@R1 5.5.2 Reading the Data of a Specific Entry This example reads the data section of a specific cache entry. The longword indicated in the data field of the data array in figure 5.5 is read to the register. R0 specifies the address and R1 is read. ; R1=H'F100 004C; data array access, entry=B'0000100, Way = 0, longword ; address = 3 ; MOV.L @R0,R1 ; Longword 3 is read. |
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