SH7708 datasheet(127/633 Pages) RENESAS

127 / 633 page

109

6.1.3

Pin Configuration

Table 6.1 shows the INTC pin configuration.

Table 6.1

Pin Configuration

Name

Abbreviation

I/O

Description

Nonmaskable interrupt input pin

NMI

Input of nonmaskable interrupt request

signal

Interrupt input pins

IRL3–IRL0

Input of interrupt request signals

(maskable by I3–I0 in SR)

Bus request output pin

IRQOUT

Output of signal that notifies external

devices that an interrupt or memory

refresh request has occurred

6.1.4

The INTC has the three registers listed in table 6.2.

Table 6.2

Name

Abbr.

R/W

Initial

Value*1 Address

Access

Size

Interrupt control register

ICR

R/W

H'FFFFFEE0

Interrupt priority level setting register A

IPRA

R/W

H'0000

H'FFFFFEE2

Interrupt priority level setting register B

IPRB

R/W

H'0000

H'FFFFFEE4

Notes: 1. Initialized by a power-on reset or manual reset.

2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.

6.2

Interrupt Sources

There are three types of interrupt sources: NMI, IRL, and on-chip supporting modules. Each

interrupt has a priority level (0–16) with 0 the lowest and 16 the highest. Priority level 0 masks an

interrupt.

SH7708 数据表(PDF) 127 Page - Renesas Technology Corp

SH7708 数据表(HTML) 127 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载