SH7708 datasheet(130/633 Pages) RENESAS

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6.2.3

On-Chip Supporting Module Interrupts

On-chip supporting module interrupts are generated by the following five modules:

• Timer unit (TMU)

• Realtime clock (RTC)

• Serial communication interface (SCI)

• Bus state controller (BSC)

• Watchdog timer (WDT)

Not every interrupt source is assigned a different interrupt vector. Sources are reflected on the

interrupt event register (INTEVT). It is easy to identify sources by using the values of the

INTEVT register as branch offsets (in the exception handler routine).

The priority level (from 0–15) can be set for each module by writing to interrupt priority setting

registers A–B (IPRA–IPRB).

The interrupt mask bits (I3–I0) in the status register are not affected by the on-chip supporting

module interrupt handling.

On-chip supporting module interrupt source flag and interrupt enable flag updating should only be

performed when the BL bit in the status register (SR) is set to 1. To prevent acknowledgment of an

erroneous interrupt from an interrupt source that should have been updated, first read the on-chip

peripheral register containing the relevant flag, then clear the BL bit to 0. This will secure the

necessary timing internally. When updating a number of flags, there is no problem if only the

If flag updating is performed while the BL bit is cleared to 0, the program may jump to the

interrupt service routine when the INTEVT register value is 0. In this case, interrupt handling is

initiated due to the timing relationship between the flag update and interrupt request recognition

within the chip. Processing can be continued without any problem by executing an RTE

instruction.

6.2.4

Interrupt Exception Handling and Priority

Table 6.3 lists the codes for the interrupt event register (INTEVT), and the order of interrupt

priority. Each interrupt source is assigned unique code. The start address of the interrupt handler is

common to each interrupt source. This is why, for instance, the value of INTEVT is used as offset

at the start of the interrupt handler and branched to identify the interrupt source.

The order of priority of the on-chip supporting module is set within the priority levels 0–15 at will

by using the interrupt priority level set in registers A and B (IPRA–IPRB). The order of priority of

the on-chip supporting module is set to zero by a reset.

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