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SH7708 数据表(PDF) 132 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 132 Page - Renesas Technology Corp |
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132 / 633 page ![]() 114 Table 6.4 Interrupt Exception Vectors and Rankings (cont) Interrupt Source INTEVT Code Interrupt Priority (Initial Value) IPR (Bit Numbers) Priority within IPR Setting Unit Default Priority RTC ATI*3 H'480 0–15 (0) IPRA (3–0) High High RTC PRI*4 H'4A0 0–15 (0) IPRA (3–0) ↓ RTC CUI*5 H'4C0 0–15 (0) IPRA (3–0) Low SCI ERI*6 H'4E0 0–15 (0) IPRB (7–4) High SCI RXI*7 H'500 0–15 (0) IPRB (7–4) ↓ ↓ SCI TXI*8 H'520 0–15 (0) IPRB (7–4) SCI TEI*9 H'540 0–15 (0) IPRB (7–4) Low WDT ITI H'560 0–15 (0) IPRB (15–12) — REF RCMI*10 H'580 0–15 (0) IPRB (11–8) High REF ROVI*11 H'5A0 0–15 (0) IPRB (11–8) Low Low Notes: 1. TUNI0–TUNI2: Underflow interrupts, see section 11. 2. TICPI2: Input capture interrupt, see section 11. 3. ATI: Alarm interrupt, see section 12. 4. PRI: Periodic interrupt, see section 12. 5. CUI: Carry-up interrupt, see section 12. 6. ERI: Receive error interrupt, see section 13. 7. RXI: Receive-data-full interrupt, see section 13. 8. TXI: Transmit-data-empty interrupt, see section 13. 9. TEI: Transmit-data-end interrupt, see section 13. 10. ITI: Interval timer interrupt, see section 9. 11. RCMI: Compare-match interrupt, see section 10. 12. ROVI: Refresh counter overflow interrupt, see section 10. |
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