SH7708 datasheet(129/633 Pages) RENESAS

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Table 6.3

IRL3–IRL0 Pins and Interrupt Levels

IRL3

IRL2

IRL1

IRL0

Interrupt Priority Level

Interrupt Request

0000

Level 15 interrupt request

0001

Level 14 interrupt request

0010

Level 13 interrupt request

0011

Level 12 interrupt request

0100

Level 11 interrupt request

0101

Level 10 interrupt request

0110

Level 9 interrupt request

0111

Level 8 interrupt request

1000

Level 7 interrupt request

1001

Level 6 interrupt request

1010

Level 5 interrupt request

1011

Level 4 interrupt request

1100

Level 3 interrupt request

1101

Level 2 interrupt request

1110

Level 1 interrupt request

1111

No interrupt request

A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels

sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that

no transient level on the

IRL pin change is detected. In standby mode, as the peripheral clock is

stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead.

Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed

in standby mode.

The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the

interrupt handling starts. However, the priority level can be changed to a higher one.

The interrupt mask bits (I3–I0) in the status register (SR) are not affected by

IRL interrupt

handling.

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