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SH7708 数据表(PDF) 126 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 126 Page - Renesas Technology Corp |
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126 / 633 page ![]() 108 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the INTC. REF WDT SCI RTC TMU ICR Input control Com- parator Priority identifier 3 44 Interrupt request SR IPRA–IPRB IRL3–IRL0 NMI IRQOUT Timer unit Realtime clock unit Serial communication interface Watch dog timer Memory refresh controller section of the bus state controller Interrupt control register Interrupt priority level setting registers A–B Status register TMU: RTC: SCI: WDT: REF: ICR: IPRA–IPRB: SR: (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request/ refresh request) IPR CPU Bus interface INTC 2 1 0 Figure 6.1 INTC Block Diagram |
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