SH7708 datasheet(158/633 Pages) RENESAS

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7.3.6

Cautions

1. If pre-execution is specified for one channel and post-execution for the other for the same

address, a pre-execution break will be generated but the condition match flag will be set for

both channels.

2. Do not set consecutive PC breaks for a delayed branch instruction and a delay slot instruction.

3. If a PC break (post-execution condition) is set for the TRAPA instruction, the condition match

flag will be set but a break will not be executed. The TRAP instruction will be processed

correctly.

4. If data access (address + data) is set as a break condition, and an exception is generated by the

instruction (including the delay slot for a delayed branch instruction) following that at which

that break condition was matched, the condition match flag will be set but a break will not be

executed. The exception generated after the break will be processed correctly.

5. If data access (address + data) is set as a break condition, and the instruction following that at

which that break condition was matched is a SLEEP instruction, the condition match flag will

be set but a break will not be executed. The SLEEP instruction will be processed correctly.

6. If an instruction fetch (halt after execution) is set as a break condition, and a nonmaskable

interrupt is detected at the instruction following that at which that break condition was

matched, the condition match flag will be set but a break will not be executed. The

nonmaskable interrupt will be processed correctly.

7. When a sequential break setting is made, a condition match occurs on a channel B match in a

bus cycle after that in which a channel A match occurred. Therefore, a condition match will

not be recognized if bus cycles occurring simultaneously in channel A and B are designated.

Also, since the CPU has a pipeline structure, the order of instruction fetch and data access

cycles is determined by the pipeline. With sequential conditions, therefore, the sequential

conditions will be taken as being matched as long as the respective channel conditions match

in the order in which the bus cycles occur.

8. With an emulator, the UBC is used on the emulator system side in order to implement the

emulator’s break functions. Consequently, no UBC functions can be used when an emulator is

used.

SH7708 数据表(PDF) 158 Page - Renesas Technology Corp