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SH7708 数据表(PDF) 155 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 155 Page - Renesas Technology Corp |
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155 / 633 page ![]() 137 7.3.4 Saved Program Counter (PC) Value 1. When instruction fetch (pre-execution) is set as break condition The program counter (PC) value saved in the SPC in user break interrupt handling is the address of the instruction for which the break condition matched. In this case, the fetched instruction is not executed, due to the user break interrupt generated prior to its execution. In the fetch cycle of an instruction located in the delay slot of a delayed branch instruction, a break is generated before the branch, so that the SPC value indicates the delayed branch instruction. 2. When instruction fetch (post-execution) is set as break condition The program counter (PC) value saved in the SPC in user break interrupt processing is the address of the next instruction to be executed after the instruction for which the break condition matched. In this case, the fetched instruction is executed, and a user break trap occurs before execution of the next instruction. When a delayed branch instruction is designated, the delay slot instruction is executed and a user break occurs before execution of the instruction at the branch destination. In this case, the PC value saved in the SPC is the address of the branch destination instruction. 3. When data access (address only) is set as break condition The value saved is the address of the next instruction to be executed after the instruction for which the condition matched. The condition-matching instruction is executed, and a user break trap occurs before execution of the next instruction. 4. When data access (address + data ) is set as break condition The value saved is the start address of the next instruction after the instruction for which execution has been completed when user break trap processing is initiated. When a data value is set as a break condition, the point at which the break is to be made cannot be specified. A break is executed before execution of the instruction fetched around the time of the break data access. |
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