SH7708 datasheet(153/633 Pages) RENESAS

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7.3.2

Instruction Fetch Cycle Break

1. Making an instruction fetch/read/word setting made in the break bus cycle register

(BBRA/BBRB) enables an instruction fetch cycle to be set as a break condition. In this case,

pre- or post-execution of the instruction can be selected by means of bit PCBA/PCBB in the

break control register (BRCR).

2. When instructions are fetched consecutively, 32 bits (two instructions) are fetched in one bus

cycle. In this case, although only one bus cycle is generated, breaks can be set for both

instructions by setting the start addresses of the respective instructions in the break address

registers (BARA and BARB).

3. With an instruction subject to a pre-execution break, the break is executed when it has been

confirmed that the instruction has been fetched and is to be executed. Consequently, an

overrun-fetched instruction (an instruction fetched but not executed in the event of a branch or

exception) cannot be subject to a break. If an exception when an instruction subject to a break

is fetched, exception processing is performed first, and the break is executed only when the

instruction is re-executed.

Since a delayed branch instruction and delay slot instruction are executed as a single

instruction, if a pre-execution condition is specified for the delay slot instruction, a break is

made before execution of the delayed branch instruction. However, a pre-execution break

condition cannot be specified for an RTE instruction delay slot instruction.

4. With a post-execution condition, the instruction set as the break condition is executed and a

break trap is generated before the next instruction is executed. In the same way, a break cannot

be specified for an overrun-fetch instruction. When a post-execution condition is set for a

delayed branch instruction, similarly, the break is made after executing the delay slot and

before executing the instruction at the branch destination.

5. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.

Therefore, break data need not be set for an instruction fetch cycle break.

6. Instruction fetch cycle breaks cannot be specified consecutively for a delayed branch

instruction and its delay slot.

SH7708 数据表(PDF) 153 Page - Renesas Technology Corp