SH7708 datasheet(157/633 Pages) RENESAS

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ASID = H'70, after execution of the instruction at address H'00037226 with ASID = H'80.

3. Data access cycle break condition setting

BRCR = H'0080: Independent channel A and B conditions, data break enable

Channel A:

BASRA = H'80:

ASID H'80

BARA = H'00123456:

Address H'00123456

BAMRA = H'00:

Address mask H'00

BBRA = H'0024:

Bus cycle, data access, read (operand size not

included in conditions)

Channel B:

BASRB = H'70:

ASID H'70

BARB = H'000ABCDE: Address H'000ABCDE

BAMRB = H'02:

Address mask H'02

BBRB = H'002A:

Bus cycle, data access, write, word

BDRB = H'0000A512:

Data H'0000A512, (data break enable)

BDMRB = H'00000000: Data mask H'00000000

For channel A, a user break trap occurs when ASID = H'80 and a longword read is performed

at address H'00123454, a word read is performed at address H'00123456, or a byte read is

performed at address H'00123456.

For channel B, a user break trap occurs when ASID = H'70 and H'A512 is written anywhere in

addresses H'000AB000 to H'000ABFFE.

4. Instruction fetch cycle break condition setting (example of setting error)

BRCR = H'0000: Independent channel A and B conditions, pre-execution for channel A, pre-

execution for channel B

Channel A:

BASRA = H'80:

ASID H'80

BARA = H'00027128

Address H'00027128

BAMRA = H'00:

Address mask H'00

BBRA = H'001A:

Bus cycle, instruction fetch (pre-execution),

write, word

Channel B:

BASRB = H'70:

ASID H'70

BARB = H'00031415

Address H'00031415

BAMRB = H'00:

Address mask H'00

BBRB = H'0014:

Bus cycle, instruction fetch (pre-execution),

read, (operand size not included in conditions)

BDRB = H'00000000:

Data H'00000000

BDMRB = H'00000000: Data mask H'00000000

For channel A, a user break trap does not occur since an instruction fetch is not a write cycle.

For channel B, a user break trap does not occur since an instruction fetch is performed on an

even address.

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