SH7708 datasheet(151/633 Pages) RENESAS

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Bit 10—PC Break Select A (PCBA): Selects whether to place the channel A instruction fetch

cycle break before or after instruction execution.

Bit 10: PCBA

Description

Places the channel A PC break before instruction execution.

(Initial value)

Places the channel A PC break after instruction execution.

Bits 9 and 8—Reserved: These bits always read 0. The write value should always be 0.

Bit 7—Data Break Enable B (DBEB): Selects whether to include data bus conditions in the

channel B break conditions.

Bit 7: DBEB

Description

Do not include data bus conditions in the channel B conditions.

(Initial value)

Include data bus conditions in the channel B conditions.

Note:

When the data bus is not included in the break conditions, the IDB1 and IDB0 bits of break

bus cycle register B (BBRB) should be 10 or 11.

Bit 6—PC Break Select B (PCBB): Selects whether to place the channel B instruction fetch cycle

break before or after instruction execution

Bit 6: PCBB

Description

Places the channel B PC break before instruction execution.

(Initial value)

Places the channel B PC break after instruction execution.

Bits 5 and 4—Reserved: These bits always read 0. The write value should always be 0.

Bit 3—Sequence Condition Select (SEQ): Selects whether to handle the channel A and B

conditions independently or sequentially. When set for sequential, the CMFB flag is set when the

channel B condition is matched after the channel A condition has already been matched.

Bit 3: SEQ

Description

Compare channel A and B conditions independently.

(Initial value)

Compare channel A and B conditions sequentially (channel A, then

channel B).

Bits 2 to 0—Reserved: These bits always read 0. The write value should always be 0.

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