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SH7708 数据表(PDF) 147 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 147 Page - Renesas Technology Corp |
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147 / 633 page  129 Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1 and IDA0): These bits select whether to break channel A on instruction fetch and/or data access cycles. Bit 5: IDA1 Bit 4: IDA0 Description 0 0 No conditions compared (Initial value) 1 Break on instruction fetch cycle 1 0 Break on data access cycle 1 Break on either instruction fetch or data access cycle Bits 3 and 2—Read/Write Select A (RWA1 and RWA0): These bits select whether to break channel A on read and/or write cycles. Bit 3: RWA1 Bit 2: RWA0 Description 0 0 No conditions compared (Initial value) 1 Break on read cycles 1 0 Break on write cycles 1 Break on both read and write cycles Bits 1 and 0—Operand Size Select A (SZA1 and SZA0): These bits select the bus cycle operand size as a channel A break condition. Bit 1: SZA1 Bit 0: SZA0 Description 0 0 Operand size is not a break condition (Initial value) 1 Break on byte access 1 0 Break on word access 1 Break on longword access 7.2.8 Break Bus Cycle Register B (BBRB) BBRB is the break bus cycle register for channel B. The bit configuration is the same as for BBRA. |
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