SH7708 datasheet(146/633 Pages) RENESAS

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Bits 1 and 0—Break Address Mask A1 and A0 (BAMA1 and BAMA0): These bits indicate which

of the channel A break address bits 31–0 (BAA31–BAA0) set in BARA are masked.

Bit 1: BAMA1

Bit 0: BAMA0

Description

BARA not masked; all bits included in break condition.

Lowest 10 bits masked and excluded from break condition.

Lowest 12 bits masked and excluded from break condition.

All BARA bits masked; address not included in break

condition.

7.2.6

Break Address Mask Register B (BAMRB)

BAMRB is the break address mask register for channel B. The bit configuration is the same as for

BAMRA.

7.2.7

Break Bus Cycle Register A (BBRA)

Bit:

Bit name:

—

Initial value:

R/W:

Bit:

Bit name:

—

IDA1

IDA0

RWA1

RWA0

SZA1

SZA0

Initial value:

R/W:

R/W

The break bus cycle register A (BBRA) is a 16-bit read/write register that sets the following three

channel A break conditions for channel A: (1) instruction fetch/data access, (2) read/write, and (3)

operand size. A reset initializes BBRA to H'0000.

Bits 15 to 6—Reserved: These bits always read 0. The write value should always be 0.

SH7708 数据表(PDF) 146 Page - Renesas Technology Corp

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