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SH7708 数据表(PDF) 144 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 144 Page - Renesas Technology Corp |
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144 / 633 page  126 5. Sequential use of channels A and B is set in the SEQ bit of the BRCR. When sequential use is designated, a user break occurs when the channel B conditions are matched after matching of channel A conditions. 6. When a user break occurs, the CMFA and CMFB bits in the BRCR register are set to 1. If a break is to be generated again, the CMFA and CMFB bits should be cleared to 0. 7.2 UBC Register Functions 7.2.1 Break Address Register A (BARA) Bit: 31 30 29 28 27 26 25 24 Bit name: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 Bit name: BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Bit name: BAA15 BAA14 BAA13 BAA12 BAA11 BA10 BAA9 BAA8 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Bit name: BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Break address register A (BARA) is a 32-bit read/write register that stores the virtual address of the channel A break condition. It is not initialized by a reset. Bits 31 to 0—Break Address A31 to 0 (BAA31 to BAA0): These bits store the virtual address of the channel A break condition. 7.2.2 Break Address Register B (BARB) BARB is the break address register for channel B. The bit configuration is the same as for BARA. |
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