SH7708 datasheet(141/633 Pages) RENESAS

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Section 7 User Break Controller (UBC)

7.1

Overview

The user break controller (UBC) provides functions that simplify program debugging. These

functions make it easy to design an effective self-monitoring debugger, enabling programs to be

debugged in the chip alone, without using an in-circuit emulator. Break conditions that can be set

in the UBC are instruction fetch or data read/write, data size, data content, address value, and stop

timing during instruction fetches.

7.1.1

Features

The features of the user break controller are listed below.

• Two break channels (channel A and channel B). User break interrupts can be requested using

either independent or sequential condition for the two channels (sequential breaks are channel

A, then channel B).

• Selection and setting of the following as break compare conditions:

 Address

Selection of 32-bit logical address and ASID to be compared

Address: Compare all bits, mask bottom 10 bits, mask bottom 12 bits. mask all bits

ASID: Compare all bits/mask all bits

 Data (channel B only, 32-bit maskable)

 Bus cycle: Instruction fetch/data access

 Read/write

 Operand size: byte/word/longword

• The instruction fetch cycle break can be performed before or after the instruction is executed.

• User break trap generated when break conditions are satisfied. A user-designed user break trap

routine can be run.

7.1.2

Block Diagram

Figure 7.1 shows the logical block diagram of the user break controller.

SH7708 数据表(PDF) 141 Page - Renesas Technology Corp