SH7708 datasheet(139/633 Pages) RENESAS

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121

Table 6.6

Interrupt Response Time (cont)

Number of States

Item

NMI

Peripheral

Modules

Notes

Response

time

Total

(5.5 + X)

× Icyc

+ 0.5

× Bcyc

+ 0.5

× Pcyc

(5.5 + X)

× Icyc

+ 0.5

× Bcyc

+ 2

× Pcyc

(5.5 + X)

× Icyc

+ 1.5

× Pcyc

Minimum

case*2

6.5

At 60 MHz operation:

0.10–0.14 µs

Maximum

case*3

7 + S

13 + S

10.5 + S

At 60 MHz operation:

0.23–0.34 µs (in case of

operand cache-hit)

At 60 MHz operation:

0.27–0.37 µs (when

external memory access

is performed with wait =

Icyc:

Duration of one cycle of internal clock supplied to CPU, etc.

Bcyc: Duration of one CKIO cycle

Pcyc: Duration of one cycle of peripheral clock supplied to supporting modules

Notes: 1. S also includes the memory access wait time.

The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the

memory access is a cache-hit, this requires 7 instruction execution cycles. When

external access is performed, the corresponding number of cycles must be added.

There are also instructions that perform two external memory accesses; if external

memory access is slow, the number of instruction execution cycles will increase

accordingly.

2. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1.

3. The internal clock : CKIO : peripheral clock ratio is 1 : 1 : 1/4.

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