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SH7708 数据表(PDF) 148 Page - Renesas Technology Corp |
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SH7708 数据表(HTML) 148 Page - Renesas Technology Corp |
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148 / 633 page  130 7.2.9 Break Data Register B (BDRB) Bit: 31 30 29 28 27 26 25 24 Bit name: BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 23 22 21 20 19 18 17 16 Bit name: BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 Bit name: BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit: 7 6 5 4 3 2 1 0 Bit name: BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 Initial value: — — — — — — — — R/W: R/W R/W R/W R/W R/W R/W R/W R/W Break data register B (BDRB) is a 32-bit read/write register that specifies the data that is the break condition for channel B data breaks. BDRB is not initialized by a reset. BDRB Bits 31 to 0—Break Data B31 to B0 (BDB31 to BDB0): These bits store the data that is the break condition for break channel B. When byte access has been specified by the SZB bit in the BBRB register, set the same byte data in bits BDB15–BDB8 as has been set in bits BDB7–BDB0. Bits BDB31–BDB16 are ignored when either byte or word access is specified. When the instruction fetch cycle is specified as a channel B break condition, or when the data bus is not included in the conditions according to the DBEB bit specification in BRCR (0), the BDRB value is ignored. |
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