SH7708 datasheet(189/633 Pages) RENESAS

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Bit 7—PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid

in clock operating modes 3–6. PLL circuit 1 goes on when the clock operating mode is 0–2 or 7

irrespective of the value of PLLEN.

Bit 7: PLLEN

Description

PLL circuit 1 is not used.

(Initial value)

PLL circuit 1 is used.

Bit 6—PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1

will be in standby mode at the frequency specified by the STC bit. This function is valid in clock

operating modes 3–6.

Bit 6: PSTBY

Description

PLL is not in standby mode.

(Initial value)

PLL is in standby mode.

Bits 5 and 4—Frequency Multiplication Ratio (STC1, STC0): These bits specify the frequency

multiplication ratio of PLL circuit 1.

Bit 5: STC1

Bit 4: STC0

Description

× 1

(Initial value)

× 2

× 4

Setting prohibited (do not set)

Note:

Do not set the output frequency of PLL circuit 1 higher than 60 MHz.

Bits 3 and 2—Internal Clock Frequency Division Ratio (IFC1, IFC0): These bits specify the

frequency division ratio of the internal clock with respect to the output frequency of PLL circuit 1.

When PLL circuit 1 is off or in standby mode, set

× 1.

Bit 3: IFC1

Bit 2: IFC0

Description

× 1

(Initial value)

× 1/2

× 1/4

Setting prohibited (do not set)

Note:

Do not set the internal clock frequency lower than the CKIO frequency.

SH7708 数据表(PDF) 189 Page - Renesas Technology Corp

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