SH7708 datasheet(192/633 Pages) RENESAS

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174

Bit 6: PSTBY

Description

PLL is not in standby mode.

(Initial value)

PLL is in standby mode.

9.5

Changing the Frequency

The frequency of the internal clock and peripheral clock can be changed either by changing the

multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of

these are controlled by software through the frequency control register. The methods are described

below. In modes 3–6, the frequency can also be changed by turning PLL circuit 1 on and off, as

described in section 9.6, PLL Standby Function.

9.5.1

Changing the Multiplication Rate

A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-

chip WDT counts the settling time.

1. In the initial state, the multiplication rate of PLL circuit 1 is 1.

2. Set a value that will become the specified oscillation settling time in the WDT and stop the

WDT. The following must be set:

WTCSR register TME bit = 0: WDT stops

WTCSR register CKS2–CKS0 bits: Division ratio of WDT count clock

WTCNT counter: Initial counter value

3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the

IFC1–IFC0 bits and PFC1–PFC0 bits.

4. The processor pauses internally and the WDT starts incrementing. In clock modes 0–2 and 7,

the internal and peripheral clocks both stop. In clock modes 3 and 4, only the internal clock

stops. The clock will continue to be output at the CKIO pin as long as the CKOEN bit in the

FRQCR register is set to 1.

5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins

operating again. The WDT stops after it overflows.

9.5.2

Changing the Division Ratio

The WDT will not count unless the multiplication rate is changed simultaneously.

1. In the initial state, IFC1–IFC0 = 00 and PFC1–PFC0 = 10.

2. Set the IFC1, IFC0, PFC1, and PFC0 bits to the new division ratio. The values that can be set

are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the

wrong value is set, the processor will malfunction.

3. The clock is immediately supplied at the new division ratio.

SH7708 数据表(PDF) 192 Page - Renesas Technology Corp

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