 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
H8/3003 数据表(PDF) 335 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8/3003 数据表(HTML) 335 Page - Renesas Technology Corp |
|
|
335 / 715 page  10.3 CPU Interface 10.3.1 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 10-6 and 10-7 show examples of word access to a timer counter (TCNT). Figures 10-8, 10-9, 10-10, and 10-11 show examples of byte access to TCNTH and TCNTL. Figure 10-6 Access to Timer Counter (CPU Writes to TCNT, Word) Figure 10-7 Access to Timer Counter (CPU Reads TCNT, Word) On-chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL On-chip data bus CPU H L Bus interface H L Module data bus TCNTH TCNTL 317 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
