H8SLASH3003 datasheet(331/715 Pages) RENESAS

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Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or

underflow and GRA or GRB compare match or input capture. These flags are interrupt sources

and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register

(TIER).

TSR is initialized to H'F8 by a reset and in standby mode.

Bits 7 to 3—Reserved: Read-only bits, always read as 1.

Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.

Bit 2

OVF

Description

[Clearing condition]

(Initial value)

Read OVF when OVF = 1, then write 0 in OVF

[Setting condition]

TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*

Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs

only under the following conditions:

1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)

2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in

TFCR)

Bit

Initial value

Read/Write

—

OVF

R/(W)

Reserved bits

Note:

Only 0 can be written, to clear the flag.

IMFB

R/(W)

IMFA

R/(W)

Overflow flag

Status flag indicating

overflow or underflow

Input capture/compare match flag B

Status flag indicating GRB compare

match or input capture

Input capture/compare match flag A

Status flag indicating GRA compare

match or input capture

313

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