H8SLASH3003 datasheet(330/715 Pages) RENESAS

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Bit 3—Reserved: Read-only bit, always read as 1.

Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.

Bit 2

Bit 1

Bit 0

IOA2

IOA1

IOA0

Function

No output at compare match

(Initial value)

0 output at GRA compare match*1

1 output at GRA compare match*1

Output toggles at GRA compare match

(1 output in channel 2)*1, *2

GRA captures rising edge of input

GRA captures falling edge of input

GRA captures both edges of input

Notes: 1. After a reset, the output is 0 until the first compare match.

2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output

instead.

10.2.12 Timer Status Register (TSR)

TSR is an 8-bit register. The ITU has five TSRs, one in each channel.

Channel

Abbreviation

Function

TSR0

Indicates input capture, compare match, and overflow status

TSR1

TSR2

TSR3

TSR4

GRA is an output

compare register

GRA is an input

capture register

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