H8SLASH3003 datasheet(333/715 Pages) RENESAS

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10.2.13 Timer Interrupt Enable Register (TIER)

TIER is an 8-bit register. The ITU has five TIERs, one in each channel.

Channel

Abbreviation

Function

TIER0

Enables or disables interrupt requests.

TIER1

TIER2

TIER3

TIER4

Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt

requests and general register compare match and input capture interrupt requests.

TIER is initialized to H'F8 by a reset and in standby mode.

Bits 7 to 3—Reserved: Read-only bits, always read as 1.

Bit

Initial value

Read/Write

—

OVIE

R/W

IMIEB

R/W

IMIEA

R/W

Reserved bits

Overflow interrupt enable

Enables or disables OVF

interrupts

Input capture/compare match

interrupt enable B

Enables or disables IMFB interrupts

Input capture/compare match

interrupt enable A

Enables or disables IMFA

interrupts

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