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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 327 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 327 Page - Renesas Technology Corp |
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327 / 715 page  Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description 0 0 TCNT is not cleared (Initial value) 1 TCNT is cleared by GRA compare match or input capture*1 1 0 TCNT is cleared by GRB compare match or input capture*1 1 Synchronous clear: TCNT is cleared in synchronization with other synchronized timers*2 Notes: 1. TCNT is cleared by compare match when the general register functions as a compare match register, and by input capture when the general register functions as an input capture register. 2. Selected in the timer synchro register (TSNC). Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges when an external clock source is used. Bit 4 Bit 3 CKEG1 CKEG0 Description 0 0 Count rising edges (Initial value) 1 Count falling edges 1 — Count both edges When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored. Phase counting takes precedence. 309 |
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