H8SLASH3003 datasheet(325/715 Pages) RENESAS

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When a general register is used as an input capture register, rising edges, falling edges, or both

edges of an external input capture signal are detected and the current TCNT value is stored in the

general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The

valid edge or edges of the input capture signal are selected in TIOR.

TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized

PWM mode.

General registers are linked to the CPU by an internal 16-bit bus and can be written or read by

either word access or byte access.

General registers are initialized to the output compare function (with no output signal) by a reset

and in standby mode. The initial value is H'FFFF.

10.2.9 Buffer Registers (BRA, BRB)

The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3

and 4.

Channel

Abbreviation

Function

BRA3, BRB3

Used for buffering

BRA4, BRB4

• When the corresponding GRA or GRB functions as an output

compare register, BRA or BRB can function as an output compare

buffer register: the BRA or BRB value is automatically transferred

to GRA or GRB at compare match

• When the corresponding GRA or GRB functions as an input

capture register, BRA or BRB can function as an input capture

buffer register: the GRA or GRB value is automatically transferred

to BRA or BRB at input capture

A buffer register is a 16-bit readable/writable register that is used when buffering is selected.

Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.

The buffer register and general register operate as a pair. When the general register functions as an

output compare register, the buffer register functions as an output compare buffer register. When

the general register functions as an input capture register, the buffer register functions as an input

capture buffer register.

Bit

Initial value

Read/Write

R/W

307

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