H8SLASH3003 datasheet(321/715 Pages) RENESAS

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Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.

Bit 2

EB4

Description

TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates as

a generic input/output pin).

If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.

TIOCB4 is enabled for output according to TIOR4 and TFCR settings

(Initial value)

Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.

Bit 1

EA4

Description

TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4

operates as a generic input/output pin).

If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.

TIOCA4 is enabled for output according to TIOR4, TMDR, and

(Initial value)

TFCR settings

Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.

Bit 0

EA3

Description

TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3

operates as a generic input/output pin).

If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.

TIOCA3 is enabled for output according to TIOR3, TMDR, and

(Initial value)

TFCR settings

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H8/3003 数据表(PDF) 321 Page - Renesas Technology Corp