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H8/3003 数据表(PDF) 323 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 323 Page - Renesas Technology Corp |
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323 / 715 page ![]() Bits 3 and 2—Reserved: Read-only bits, always read as 1. Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 Description 0 TIOCA3, TIOCA4, and TIOCB4 outputs are inverted 1 TIOCA3, TIOCA4, and TIOCB4 outputs are not inverted (Initial value) Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 0 OLS3 Description 0 TIOCB3, TOCXA4, and TOCXB4 outputs are inverted 1 TIOCB3, TOCXA4, and TOCXB4 outputs are not inverted (Initial value) 10.2.7 Timer Counters (TCNT) TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel. Channel Abbreviation Function 0 TCNT0 Up-counter 1 TCNT1 2 TCNT2 Phase counting mode: up/down-counter Other modes: up-counter 3 TCNT3 4 TCNT4 Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in the timer control register (TCR). Bit Initial value Read/Write 14 0 R/W 12 0 R/W 10 0 R/W 8 0 R/W 6 0 R/W 0 0 R/W 4 0 R/W 2 0 R/W 15 0 R/W 13 0 R/W 11 0 R/W 9 0 R/W 7 0 R/W 1 0 R/W 5 0 R/W 3 0 R/W Complementary PWM mode: up/down-counter Other modes: up-counter 305 |
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