H8SLASH3003 datasheet(451/715 Pages) RENESAS

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13.2.6 Serial Control Register (SCR)

SCR enables the SCI transmitter and receiver, enables or disables serial clock output in

asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.

The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby

mode.

Bit

Initial value

Read/Write

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Transmit interrupt enable

Enables or disables transmit-data-empty interrupts (TXI)

Clock enable 1/0

These bits select the

SCI clock source

Receive interrupt enable

Enables or disables receive-data-full interrupts (RXI) and

receive-error interrupts (ERI)

Transmit enable

Enables or disables the transmitter

Receive enable

Enables or disables the receiver

Multiprocessor interrupt enable

Enables or disables multiprocessor

interrupts

Transmit end interrupt enable

Enables or disables transmit-

end interrupts (TEI)

433

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