H8SLASH3003 datasheet(452/715 Pages) RENESAS

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Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt

(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from

TDR to TSR.

Bit 7

TIE

Description

Transmit-data-empty interrupt request (TXI) is disabled*

(Initial value)

Transmit-data-empty interrupt request (TXI) is enabled

Note: * TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then

clearing it to 0; or by clearing the TIE bit to 0.

Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)

requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to

RDR; also enables or disables the receive-error interrupt (ERI).

Bit 6

RIE

Description

Receive-end (RXI) and receive-error (ERI) interrupt requests are disabled (Initial value)

Receive-end (RXI) and receive-error (ERI) interrupt requests are enabled

Note: * RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER,

PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0.

Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations.

Bit 5

Description

Transmitting disabled*1

(Initial value)

Transmitting enabled*2

Notes: 1. The TDRE bit is locked at 1 in SSR.

2. In the enabled state, serial transmitting starts when the TDRE bit in SSR is cleared to 0

after writing of transmit data into TDR. Select the transmit format in SMR before setting

the TE bit to 1.

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H8/3003 数据表(PDF) 452 Page - Renesas Technology Corp