H8SLASH3003 datasheet(456/715 Pages) RENESAS

456 / 715 page

The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,

and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The

TEND and MPB flags are read-only bits that cannot be written.

SSR is initialized to H'84 by a reset and in standby mode.

Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data

from TDR into TSR and the next serial transmit data can be written in TDR.

Bit 7

TDRE

Description

TDR contains valid transmit data

[Clearing conditions]

Software reads TDRE while it is set to 1, then writes 0.

The DMAC writes data in TDR.

TDR does not contain valid transmit data

(Initial value)

[Setting conditions]

The chip is reset or enters standby mode.

The TE bit in SCR is cleared to 0.

TDR contents are loaded into TSR, so new data can be written in TDR.

Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.

Bit 6

RDRF

Description

RDR does not contain new receive data

(Initial value)

[Clearing conditions]

The chip is reset or enters standby mode.

Software reads RDRF while it is set to 1, then writes 0.

The DMAC reads data from RDR.

RDR contains new receive data

[Setting condition]

When serial data is received normally and transferred from RSR to RDR.

Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by

clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still

set to 1 when reception of the next data ends, an overrun error occurs and receive data is

lost.

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