H8SLASH3003 datasheet(457/715 Pages) RENESAS

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Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an

overrun error.

Bit 5

ORER

Description

Receiving is in progress or has ended normally

(Initial value)*1

[Clearing conditions]

The chip is reset or enters standby mode.

Software reads ORER while it is set to 1, then writes 0.

A receive overrun error occurred*2

[Setting condition]

Reception of the next serial data ends when RDRF = 1.

Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its

previous value.

2. RDR continues to hold the receive data before the overrun error, so subsequent receive

data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In

synchronous mode, serial transmitting is also disabled.

Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing

error in asynchronous mode.

Bit 4

FER

Description

Receiving is in progress or has ended normally

(Initial value)*1

[Clearing conditions]

The chip is reset or enters standby mode.

Software reads FER while it is set to 1, then writes 0.

A receive framing error occurred*2

[Setting condition]

The stop bit at the end of receive data is checked and found to be 0.

Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous

value.

2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not

checked. When a framing error occurs the SCI transfers the receive data into RDR but

does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set

to 1. In synchronous mode, serial transmitting is also disabled.

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