H8SLASH3003 datasheet(494/715 Pages) RENESAS

494 / 715 page

Figure 13-20 Sample Flowchart for Serial Transmitting

Yes

Initialize

Start transmitting and receiving

Read TDRE flag in SSR

TDRE = 1?

Write transmit data in TDR and

clear TDRE flag to 0 in SSR

RDRF = 1?

Read RDRF flag in SSR

Read receive data from RDR

and clear RDRF flag to 0 in SSR

Read ORER flag in SSR

ORER = 1?

End of transmitting and

receiving?

SCI initialization: the transmit data

output function of the TxD pin and

receive data input function of the

RxD pin are selected, enabling

simultaneous transmitting and

receiving.

SCI status check and transmit

data write: read SSR, check that

the TDRE flag is 1, then write

transmit data in TDR and clear

the TDRE flag to 0.

Error handling

Note: * When switching from transmitting or receiving to simultaneous

transmitting and receiving, clear the TE and RE bits both to 0,

then set the TE and RE bits both to 1.

Clear TE and RE bits to 0 in SCR

End

Notification that the TDRE flag has

changed from 0 to 1 can also be

given by the TXI interrupt.

Receive error handling: if a receive

error occurs, read the ORER flag in

SSR, then after executing the neces-

sary error handling, clear the ORER

flag to 0.

Neither transmitting nor receiving

can resume while the ORER flag

remains set to 1.

SCI status check and receive

data read: read SSR, check that

the RDRF flag is 1, then read

receive data from RDR and clear

the RDRF flag to 0. Notification

that the RDRF flag has changed

from 0 to 1 can also be given

by the RXI interrupt.

To continue transmitting and

receiving serial data: check the

RDRF flag, read RDR, and clear

the RDRF flag to 0 before the

MSB (bit 7) of the current frame

is received. Also check that the

TDRE flag is (bit 7) of the current

frame is received. Also check that

the TDRE flag is set to 1, indicat-

ing that data can be written, write

data in TDR, then clear the TDRE

flag to 0 before the MSB (bit 7) of

the current frame is transmitted.

When the DMAC is activated by

a transmit-data-empty interrupt

request (TXI) to write data in TDR,

the TDRE flag is checked and

cleared automatically. When the

DMAC is activated by a receive-

data-full interrupt request (RXI) to

read RDR, the RDRF flag is

cleared automatically.

476

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