H8SLASH3003 datasheet(497/715 Pages) RENESAS

497 / 715 page

Break Detection and Processing: Break signals can be detected by reading the RxD pin directly

when a framing error (FER) is detected. In the break state the input from the RxD pin consists of

all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the

SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.

Sending a Break Signal: When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the

level and direction (input or output) of which are determined by DR and DDR bits. This feature

can be used to send a break signal.

After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE

bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR

bits should therefore both be set to 1 beforehand.

To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.

When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the

TxD pin becomes an output port outputting the value 0.

Receive Error Flags and Transmitter Operation (Synchronous Mode Only): When a receive

error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE

flag is clear to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that

clearing the RE bit to 0 does not clear the receive error flags to 0.

Receive Data Sampling Timing in Asynchronous Mode and Receive Margin: In asynchronous

mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI

synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive

data is latched at the rising edge of the eighth base clock pulse. See figure 13-21.

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H8/3003 数据表(PDF) 497 Page - Renesas Technology Corp