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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8/3003 数据表(PDF) 498 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 498 Page - Renesas Technology Corp |
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498 / 715 page  Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as in equation (1). ...................(1) M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2). D = 0.5, F = 0 = 46.875%.................................................................................................(2) This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Internal base clock Receive data (RxD) Synchronization sampling timing Data sampling timing 0 7 15 0 7 15 0 D0 D1 8 clocks 16 clocks Start bit M = | (0.5 – ) – (L – 0.5) F – (1 + F) | 100% 1 2N | D – 0.5 | N × 480 M = (0.5 – ) 1 2 × 16 × 100% |
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