H8SLASH3003 datasheet(529/715 Pages) RENESAS

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Section 17 Power-Down State

17.1 Overview

The H8/3003 has a power-down state that greatly reduces power consumption by halting CPU

functions. The power-down state includes the following three modes:

•

Sleep mode

•

Software standby mode

•

Hardware standby mode

Table 17-1 indicates the methods of entering and exiting these power-down modes and the status

of the CPU and on-chip supporting modules in each mode.

Table 17-1 Power-Down State

State

Entering

CPU

Refresh

Supporting

I/O

Exiting

Mode

Conditions

Clock

CPU

Registers DMAC Controller

Functions

RAM

Ports

Conditions

Sleep

SLEEP instruc- Active

Halted

Held

Active

Held

• Interrupt

mode

tion executed

•

RES

while SSBY = 0

•

STBY

in SYSCR

Software

SLEEP instruc- Halted

Halted

Held

Halted

Held

• NMI

standby

tion executed

and

• IRQ0 to IRQ2

mode

while SSBY = 1

reset

held*1

reset

•

RES

in SYSCR

•

STBY

Hardware Low input at

Halted

Undeter

Halted

Held*2 High

•

STBY

standby

STBY pin

mined

and

impedance •

RES

mode

reset

Notes: 1. The refresh timer counter (RTCNT) and bits 7 and 6 of the refresh timer control/status register (RTMCSR) are

initialized. Other bits and registers hold their previous states.

2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware

standby mode.

Legend

SYSCR: System control register

SSBY:

Software standby bit

511

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