H8SLASH3003 datasheet(530/715 Pages) RENESAS

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17.2 Register Configuration

The H8/3003’s system control register (SYSCR) controls the power-down state. Table 17-2

summarizes this register.

Table 17-2 Control Register

Address*

Name

Abbreviation

R/W

Initial Value

H'FFF2

System control register

SYSCR

R/W

H'0B

Note: * Lower 16 bits of the address.

17.2.1 System Control Register (SYSCR)

SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control

the power-down state. For information on the other SYSCR bits, see section 3.3, System Control

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

Software standby

Enables transition to

software standby mode

RAM enable

Standby timer select 2 to 0

These bits select the

waiting time at exit from

software standby mode

User bit enable

NMI edge select

Reserved bit

512

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