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H8/3003 数据表(PDF) 684 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 684 Page - Renesas Technology Corp |
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684 / 715 page ![]() ISR—IRQ Status Register H'F6 Interrupt controller Bit Initial value Read/Write 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ to IRQ flags Bits 7 to 0 0 1 Setting and Clearing Conditions IRQ7F to IRQ0F [Clearing conditions] Read IRQnF when IRQnF = 1, then write 0 in IRQnF. IRQnSC = 0, input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. [Setting conditions] IRQnSC = 0 and input is low. IRQnSC = 1 and input changes from high to low. (n = 7 to 0) IRQn IRQn IRQn 70 Note: Only 0 can be written, to clear the flag. * 666 |
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