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H8/3003 数据表(PDF) 219 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 219 Page - Renesas Technology Corp |
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219 / 715 page ![]() Table 8-7 Register Functions in Idle Mode Function Activated by SCI Receive- Data-Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Held fixed address address source address register register Source Destination Source or Held fixed address address destination register register address Transfer counterNumber of Decremented transfers once per transfer until H'0000 is reached and transfer ends Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. MAR and IOAR are not incremented or decremented. Figure 8-4 illustrates how idle mode operates. Figure 8-4 Operation in Idle Mode 23 0 MAR All 1s IOAR 23 0 15 0 ETCR 7 Transfer 1 byte or word is transferred per request IOAR MAR 201 |
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