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H8/3003 数据表(PDF) 221 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 221 Page - Renesas Technology Corp |
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221 / 715 page ![]() 8.4.4 Repeat Mode Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable timing pattern controller (TPC) in synchronization, for example, with ITU compare match. Repeat mode can be selected for each channel independently. One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number of these transfers are executed. One address is specified in the memory address register (MAR), the other in the I/O address register (IOAR). At the end of the designated number of transfers, MAR and ETCR are restored to their original values and operation continues. The direction of transfer is determined automatically from the activation source. The transfer is from the address specified in IOAR to the address specified in MAR if activated by an SCI receive-data-full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise. Table 8-8 indicates the register functions in repeat mode. Table 8-8 Register Functions in Repeat Mode Function Activated by SCI Receive- Data-Full Other Register Interrupt Activation Initial Setting Operation Destination Source Destination or Incremented or address address source address decremented at register register each transfer until ETCRH reaches H'0000, then restored to initial value Source Destination Source or Held fixed address address destination register register address Transfer counter Number of Decremented once transfers per transfer unti H'0000 is reached, then reloaded from ETCRL Initial transfer count Number of Held fixed transfers Legend MAR: Memory address register IOAR: I/O address register ETCR: Execute transfer count register 23 0 MAR All 1s IOAR 23 0 70 ETCRH 7 70 ETCRL 203 |
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