H8SLASH3003 datasheet(280/715 Pages) RENESAS

280 / 715 page

Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select

input or output for each pin in port A.

A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input

pin if this bit is cleared to 0.

PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.

PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode

it retains its previous setting, so if a PADDR bit is set to 1, the corresponding pin maintains its

output state in software standby mode.

Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores data for

pins PA7 to PA0.

When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is

returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin

level is read.

PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it

retains its previous setting.

Bit

Initial value

Read/Write

PA DDR

Port A data direction 7 to 0

These bits select input or output for port A pins

PA DDR

Bit

Initial value

Read/Write

R/W

Port A data 7 to 0

These bits store data for port A pins

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H8/3003 数据表(PDF) 280 Page - Renesas Technology Corp