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H8/3003 数据表(PDF) 306 Page - Renesas Technology Corp |
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H8/3003 数据表(HTML) 306 Page - Renesas Technology Corp |
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306 / 715 page ![]() Figure 10-5 Block Diagram of Channel 4 Legend TCNT4: GRA4, GRB4: BRA4, BRB4: TCR4: TIOR4: TIER4: TSR4: Timer counter 4 (16 bits) General registers A4 and B4 (input capture/output compare registers) (16 bits 2) Buffer registers A4 and B4 (input capture/output compare buffer registers) (16 bits 2) Timer control register 4 (8 bits) Clock selector Comparator Control logic Module data bus × TCLKA to TCLKD ø, ø/2, ø/4, ø/8 Timer I/O control register 4 (8 bits) Timer interrupt enable register 4 (8 bits) Timer status register 4 (8 bits) × TOCXA4 TOCXB4 TIOCA4 TIOCB4 IMIA4 IMIB4 OVI4 288 |
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