H8SLASH3003 datasheet(308/715 Pages) RENESAS

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10.1.4 Register Configuration

Table 10-3 summarizes the ITU registers.

Table 10-3 ITU Registers

Abbre-

Initial

Channel

Address*1

Name

viation

R/W

Value

Common

H'FF60

Timer start register

TSTR

R/W

H'E0

H'FF61

Timer synchro register

TSNC

R/W

H'E0

H'FF62

Timer mode register

TMDR

R/W

H'80

H'FF63

Timer function control register

TFCR

R/W

H'C0

H'FF90

Timer output master enable register

TOER

R/W

H'FF

H'FF91

Timer output control register

TOCR

R/W

H'FF

H'FF64

Timer control register 0

TCR0

R/W

H'80

H'FF65

Timer I/O control register 0

TIOR0

R/W

H'88

H'FF66

Timer interrupt enable register 0

TIER0

R/W

H'F8

H'FF67

Timer status register 0

TSR0

R/(W)*2

H'F8

H'FF68

Timer counter 0 (high)

TCNT0H

R/W

H'00

H'FF69

Timer counter 0 (low)

TCNT0L

R/W

H'00

H'FF6A

General register A0 (high)

GRA0H

R/W

H'FF

H'FF6B

General register A0 (low)

GRA0L

R/W

H'FF

H'FF6C

General register B0 (high)

GRB0H

R/W

H'FF

H'FF6D

General register B0 (low)

GRB0L

R/W

H'FF

H'FF6E

Timer control register 1

TCR1

R/W

H'80

H'FF6F

Timer I/O control register 1

TIOR1

R/W

H'88

H'FF70

Timer interrupt enable register 1

TIER1

R/W

H'F8

H'FF71

Timer status register 1

TSR1

R/(W)*2

H'F8

H'FF72

Timer counter 1 (high)

TCNT1H

R/W

H'00

H'FF73

Timer counter 1 (low)

TCNT1L

R/W

H'00

H'FF74

General register A1 (high)

GRA1H

R/W

H'FF

H'FF75

General register A1 (low)

GRA1L

R/W

H'FF

H'FF76

General register B1 (high)

GRB1H

R/W

H'FF

H'FF77

General register B1 (low)

GRB1L

R/W

H'FF

Notes: 1. The lower 16 bits of the address are indicated.

2. Only 0 can be written, to clear flags.

290

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