H8SLASH3003 datasheet(314/715 Pages) RENESAS

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10.2.3 Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also

selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.

TMDR is initialized to H'80 by a reset and in standby mode.

Bit 7—Reserved: Read-only bit, always read as 1.

Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in

phase counting mode.

Bit 6

MDF

Description

Channel 2 operates normally

(Initial value)

Channel 2 operates in phase counting mode

Bit

Initial value

Read/Write

—

MDF

R/W

FDIR

R/W

PWM4

R/W

PWM3

R/W

PWM0

R/W

PWM2

R/W

PWM1

R/W

Reserved bit

PWM mode 4 to 0

These bits select PWM

mode for channels 4 to 0

Phase counting mode flag

Selects phase counting mode for channel 2

Flag direction

Selects the setting condition for the overflow

flag (OVF) in timer status register 2 (TSR2)

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