AT89C5122D-RDRUM datasheet(118/208 Pages) ATMEL

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118

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Reset Value = 0000 0000b

Reset Value = 1000 0000b when UEPNUM = 0

Reset Value = 0000 0000b otherwise

Table 68.

USB Endpoint Number - UEPNUM (S:C7h)

EPNUM3

EPNUM2

EPNUM1

EPNUM0

Bit Number

Bit Mnemonic

Description

7 - 4

Reserved

The value read from these bits is always 0. Do not change these bits.

3 - 0

EPNUM[3:0]

Endpoint Number

Set this field with the number of the endpoint which should be accessed when reading or writing to, USB Byte

Count Register X (X=EPNUM set in UEPNUM Register) - UBYCTX (S:E2h) or USB Endpoint X Control Register -

UEPCONX (S:D4h). This value can be 0, 1, 2, 3, 4, 5 or 6.

Table 69.

USB Endpoint X Control Register - UEPCONX (S:D4h)

EPEN

NAKIEN

NAKOUT

NAKIN

DTGL

EPDIR

EPTYPE1

EPTYPE0

Bit Number

Bit Mnemonic

Description

EPEN

Endpoint Enable

Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will always be enabled after

a hardware or USB bus reset and participate in the device configuration.

Clear this bit to disable the endpoint according to the device configuration.

6NAKIEN

NAK Interrupt Enable

Set this bit to enable NAKIN and NAKOUT Interrupt.

Clear this bit to disable NAKIN and NAKOUT Interrupt.

5NAKOUT

NAK OUT Sent

This bit is set by hardware when the a NAK handshake is sent by the USB controller to an OUT request from

the Host. This generates an interrupt if the NAKIEN bit is set.

This bit shall be cleared by software.

4NAKIN

NAK IN Sent

This bit is set by hardware when the a NAK handshake is sent by the USB controller to an IN request from the

Host. This generates an interrupt if the NAKIEN bit is set.

This bit shall be cleared by software.

3DTGL

Data Toggle (Read-only)

This bit is set by hardware when a valid DATA0 packet is received and accepted.

This bit is cleared by hardware when a valid DATA1 packet is received and accepted.

2EPDIR

Endpoint Direction

Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.

Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.

This bit has no effect for Control endpoints.

1-0

EPTYPE[1:0]

Endpoint Type

Set this field according to the endpoint configuration (Endpoint 0 will always be configured as control):

00Control endpoint

01Isochronous endpoint

10Bulk endpoint

11Interrupt endpoint

AT89C5122D-RDRUM 数据表(PDF) 118 Page - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 118 Page - ATMEL Corporation

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