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AT89C5122D-RDRUM 数据表(PDF) 122 Page - ATMEL Corporation |
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AT89C5122D-RDRUM 数据表(HTML) 122 Page - ATMEL Corporation |
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122 / 208 page  122 AT83R5122, AT8xC5122/23 4202F–SCR–07/2008 Reset Value = 0000 0000b Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only) 765 432 10 - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number Bit Mnemonic Description 7- Reserved The value read from these bits is always 0. Do not change this bit. 6EP6INT Endpoint 6 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 6. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP6INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. 5EP5INT Endpoint 5 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 5. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP5INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. 4EP4INT Endpoint 4 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 4. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP4INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. 3EP3INT Endpoint 3 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 3. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP3INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. 2EP2INT Endpoint 2 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 2. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP2INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. 1EP1INT Endpoint 1 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 1. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP1INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. 0EP0INT Endpoint 0 Interrupt This bit is set by hardware when an interrupt has been detected on the endpoint 0. The interrupt sources are part of UEPSTAX register and can be : TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP0INTE bit in the UEPIEN register is set. This bit is cleared by hardware when all the interrupt sources are cleared. |
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