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AT89C5122D-RDRUM 数据表(PDF) 133 Page - ATMEL Corporation

部件名 AT89C5122D-RDRUM
功能描述  C51 Microcontroller with USB and Smart Card Reader Interfaces
PDF  208 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 133 Page - ATMEL Corporation

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133
AT83R5122, AT8xC5122/23
4202F–SCR–07/2008
Registers
Reset Value = 0000 0000b (Bit addressable)
Table 77.
Serial Control Register - SCON (98h)
76543210
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic Description
7
FE
Framing Error bit (SMOD0=1
)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 in PCON register must be set to enable access to the FE bit
SM0
Serial Port Mode bit 0 (SMOD0=0
)
Refer to SM1 for serial port mode selection.
SMOD0 in PCON register must be cleared to enable access to the SM0 bit
6SM1
Serial port Mode bit 1
SM0
SM1
Mode
DescriptionBaud Rate
0
0
0
Shift Register FCk_IDLE/6
0
1
1
8-bit UARTVariable
1
0
2
9-bit UARTFCK_IDLE /32 or /16
1
1
3
9-bit UARTVariable
5SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.
This bit should be cleared in mode 0.
4REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2RB8
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
This bit can aslo be set by software.
0RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 65 and Figure
66 in the other modes.
This bit can aslo be set by software.



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