AT89C5122D-RDRUM datasheet(135/208 Pages) ATMEL

135 / 208 page

135

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Serial Port Interface

(SPI)

Only for AT8xC5122.

The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous,

serial communication between the MCU and peripheral devices, including other MCUs.

Features

Features of the SPI module include the following:

•

Full-duplex, three-wire synchronous transfers

•

Master or Slave operation

•

Eight programmable Master clock rates

•

Serial clock with programmable polarity and phase

•

Master Mode fault error flag with MCU interrupt capability

•

Write collision flag protection

Signal Description

Figure 82 shows a typical SPI bus configuration using one Master controller and many

Slave peripherals. The bus is made of three wires connecting all the devices:

Figure 82.

Typical SPI Bus

The Master device selects the individual Slave devices by using four pins of a parallel

port to control the four SS pins of the Slave devices.

Master Output Slave Input

(MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device.

The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,

it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word)

is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output

(MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device.

The MISO line is used to transfer data in series from the Slave to the Master. Therefore,

it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit

word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out the devices

through their MOSI and MISO lines. It is driven by the Master for eight clock cycles

which allows to exchange one byte on the serial lines.

Slave 1

MISO

MOSI

SCK

Slave 3

Slave 4

Slave 2

VDD

Master

AT89C5122D-RDRUM 数据表(PDF) 135 Page - ATMEL Corporation

AT89C5122D-RDRUM 数据表(HTML) 135 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载